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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10559469 B1

PDFFull Text
Date of Patent:
Feb. 11, 2020

Filed:

Apr. 21, 2015

Dual pocket approach in pfets with embedded si-ge source/drain

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Younsung Choi, Allen, TX (US);

Assignee:

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);

Attorneys:

Jacqueline J. Garner

Charles A. Brill

Frank D. Cimino

Primary Examiner:

Galina G Yushina

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/225 (2006.01); H01L 29/40 (2006.01); H01L 29/51 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2652 (2013.01); H01L 21/2253 (2013.01); H01L 21/26586 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/1045 (2013.01); H01L 29/1083 (2013.01); H01L 29/408 (2013.01); H01L 29/6659 (2013.01); H01L 29/66492 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01); H01L 29/7833 (2013.01); H01L 29/7836 (2013.01); H01L 29/165 (2013.01); H01L 29/517 (2013.01); H01L 29/7848 (2013.01);
Abstract

A p-type metal oxide semiconductor field effect transistor (PFET) includes a p-type silicon substrate and an n-type well formed in the p-type silicon substrate. The PFET also comprises a p-type source formed in the n-type well, a p-type drain formed in the n-type well, and dual pockets implanted in the n-type well and coupled to the source and drain. The dual pockets comprise a first pocket with first arsenic n-type dopants and a second pocket with second arsenic n-type dopants.

Find Patent Forward Citations

Choi, Younsung. (2020). Dual pocket approach in pfets with embedded si-ge source/drain (U.S. Patent No. 10559469). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10559469

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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