The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2018
Filed:
Sep. 03, 2015
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Younsung Choi, Allen, TX (US);
Deborah J. Riley, Murphy, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/823412 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/66492 (2013.01); H01L 29/66636 (2013.01); H01L 29/165 (2013.01); H01L 29/78 (2013.01); H01L 29/7833 (2013.01);
Abstract
An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.