The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Jul. 07, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Himadri Sekhar Pal, Allen, TX (US);

Shashank S. Ekbote, Allen, TX (US);

Youn Sung Choi, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/167 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/823418 (2013.01); H01L 21/823456 (2013.01); H01L 29/0847 (2013.01); H01L 29/1045 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01); H01L 29/42372 (2013.01); H01L 29/6659 (2013.01); H01L 29/66537 (2013.01); H01L 29/66659 (2013.01); H01L 29/7833 (2013.01); H01L 29/7835 (2013.01); H01L 29/7836 (2013.01); H01L 21/26506 (2013.01);
Abstract

An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.


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