Texas Instruments Corporation

Qualcomm Incorporated

Other

Shashank Sureshchandra Ekbote

Youn Sung Choi

Borna J Obradovic

Haowen Bu

Kwan-Yong Lim

Younsung Choi

Ebenezer Eshun

Himadri Sekhar Pal

Freidoon Mehrad

Greg Charles Baldwin

Ukjin Roh

James Walter Blatchford

Kamel Benaissa

Gregory Charles Baldwin

Mark R Visokay

Shaofeng Yu

Rajesh B Khamankar

Srinivasan Chakravarthi

Shaoping Tang

Rongtian Zhang

Xia Li

Amitabh Jain

Periannan Chidambaram

Lindsey H Hall

Deborah J Riley

Song Zhao

Ajith Varghese

Zhihao Chen

Craig Henry Huffman

Juanita DeLoach

Brian M Trentman

Samit Sengupta

Richard P Rouse

A 3D vertically integrated FET for CMOS cell circuits is disclosed. Vertically integrating FETs for a 3D cell circuit reduces the footprint size of an IC chip. To reduce a CMOS cell circuit footprint, a PFET and an NFET are vertically integrated by stacking a second semiconductor layer including a second FET above a first semiconductor layer including a first FET, such that the channel structure of the second FET overlaps the channel structure of the first FET. The first FET may be an NFET, and the second FET may be a PFET, or vice versa. The longitudinal axis of the first FET channel structure may extend in a first plane parallel to a second plane including the longitudinal axis of the second FET channel structure. The longitudinal axes may be parallel or at an angle to each other, such that the second channel structure overlaps the first channel structure.

Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits

Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail to distribute a first supply voltage to a Pwell region of corresponding SRAM bit cell rows. The SRAM strap cell also includes an N-type doped well (Nwell) tap electrically coupled to a second supply rail to distribute a second supply voltage to an Nwell region of corresponding SRAM bit cell rows. In one exemplary aspect, the Nwell tap can include multiple supply contacts used to couple the second supply rail to the SRAM strap cell to reduce mechanical stress in the Nwell tap. In another exemplary aspect, the Pwell tap can include non-active gates disposed across multiple Fins to stabilize the Fins and reduce or avoid mechanical stress in the Pwell tap.

Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells

Selective epitaxial growth is used to form a hetero-structured source/drain region to fill an etched recess in a silicon fin for an n-type FinFET device.

FinFET with reduced series total resistance

Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.

Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout

An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Method to form silicide and contact at embedded epitaxial facet

A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.

Dummy gate placement methodology to enhance integrated circuit performance

An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.

Integration of analog transistor

Fin Field Effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions are disclosed. In one aspect, a FinFET is provided that includes a substrate and a Fin disposed over the substrate. The Fin includes a source, a drain, and a channel region between the source and drain. A gate is disposed around the channel region. To apply stress to the channel region, a first dielectric material layer is disposed over the substrate and adjacent to one side of the Fin. A second dielectric material layer is disposed over the substrate and adjacent to another side of the Fin. The dielectric material layers apply stress along the Fin, including the channel region. The level of stress applied by the dielectric material layers is not dependent on the volume of each layer.

Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Silicide formation due to improved SiGe faceting

In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.

Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield

Growing community of inventors

Allen, TX, United States of America

Shashank Sureshchandra Ekbote