logo

For the Inventor, By the Inventor

Santa Cruz, CA, United States of America

Sean R Atsatt

This inventor holds 73 USPTO granted patents and 10 published patent applications and 8 EPO patents, primarily in Integrated Circuit Design (CPC class G06F). Top assignees: Intel Corporation, Altera Corporation, Seagate Technology Incorporated. Active years: 1998-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sean R Atsatt. Retrieved from https://idiyas.com/inventor/sean-r-atsatt

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 73 

% Patents Active = 94.5

 

Average Co-Inventor Count = 2.3

ph-index = 13

Forward Citations = 546(Granted Patents)

Forward Citations (Not Self Cited) = 523(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Santa Clara, CA (US) (2015)
  • Sana Cruz, CA (US) (2013 - 2017)
  • San Jose, CA (US) (2019 - 2021)
  • Santa Cruz, CA (US) (1998 - 2024)

Company Filing History:

goldMedal36 out of 56,322 
 
Intel Corporation
 patents
silverMedal29 out of 4,333 
 
Altera Corporation
 patents
bronzeMedal5 out of 8,748 
 
Seagate Technology Incorporated
 patents
4. 1 out of 166 
 
Ess Technology, Inc.
 patents
5. 1 out of 38 
 
Seagate Technologies, Inc.
 patents
6. 1 out of 834,513 
Other
 patents

Years Active: 1998-2026

Loading Chart...
Loading Chart...
Areas of Expertise:
Integrated Circuit
Network-On-Chip
Programmable Logic
Microsector Infrastructure
Thermal Management
Modular Periphery
Smart Memory
Dynamic Voltage Scaling
Error Rate Detection
Coarse-Grain Routing
Data Caching
Multi-Dimensional Die
73 patents (USPTO):Explore Patents
1. 12743215 - Logic fabric based on microsector infrastructure with data register having scan registers (2026-09-22),
2. 12265772 - Integrated circuit with peek and poke protection circuitry for multi-tenant usage model (2025-04-01),
3. 12248021 - Debug trace microsectors (2025-03-11),
4. 12237831 - Network-on-chip (NOC) with flexible data width (2025-02-25),
5. 12164462 - Micro-network-on-chip and microsector infrastructure (2024-12-10),
6. 12153866 - Modular periphery tile for integrated circuit device (2024-11-26),
7. 12132482 - Stacked programmable integrated circuitry with smart memory (2024-10-29),
8. 12063037 - Embedded network on chip accessible to programmable logic fabric of programmable logic device in multi-dimensional die systems (2024-08-13),
9. 12057836 - Logic fabric based on microsector infrastructure (2024-08-06),
10. 11960734 - Logic fabric based on microsector infrastructure with data register having scan registers (2024-04-16),
11. 11714941 - Modular periphery tile for integrated circuit device (2023-08-01),
12. 11700002 - Network-on-chip (NOC) with flexible data width (2023-07-11),
13. 11632112 - Integrated circuit device with separate die for programmable fabric and programmable fabric support circuitry (2023-04-18),
14. 11562101 - On-device bitstream validation (2023-01-24),
15. 11520388 - Systems and methods for integrating power and thermal management in an integrated circuit (2022-12-06),

Title: The Innovative Journey of Sean R Atsatt

Introduction:

Sean R Atsatt is a distinguished inventor based in Santa Cruz, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents:

Sean R Atsatt holds several patents in various technological domains, including artificial intelligence, renewable energy, and sustainable design.

Career Highlights:

With a career spanning over two decades, Sean R Atsatt has been at the forefront of technological advancements, leading teams to develop cutting-edge solutions that have revolutionized industries.

Collaborations:

Throughout his career, Sean R Atsatt has collaborated with leading tech companies, research institutions, and universities to drive innovation and bring transformative ideas to life.

Conclusion:

Sean R Atsatt's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…