The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Mar. 31, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sean R. Atsatt, Santa Cruz, CA (US);

Scott J. Weber, Piedmont, CA (US);

Ravi Prakash Gutala, San Jose, CA (US);

Aravind Raghavendra Dasu, Milpitas, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17772 (2020.01); H03K 19/17758 (2020.01); H03K 19/1776 (2020.01); H03K 19/17768 (2020.01); H03K 19/17796 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17758 (2020.01); H03K 19/1776 (2013.01); H03K 19/17768 (2013.01); H03K 19/17772 (2013.01); H03K 19/17796 (2013.01);
Abstract

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.


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