The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2023
Filed:
Dec. 20, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sharath Raghava, Los Gatos, CA (US);
Ankireddy Nalamalpu, Portland, OR (US);
Dheeraj Subbareddy, Portland, OR (US);
Harsha Gupta, Sunnyvale, CA (US);
James Ball, San Jose, CA (US);
Kavitha Prasad, San Jose, CA (US);
Sean R. Atsatt, Santa Cruz, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H03K 19/17736 (2020.01); H03K 19/17796 (2020.01); H04L 41/5019 (2022.01); H04L 41/5003 (2022.01);
U.S. Cl.
CPC ...
H03K 19/17736 (2013.01); H03K 19/17796 (2013.01); H04L 41/5019 (2013.01); H04L 41/5003 (2013.01);
Abstract
Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.