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For the Inventor, By the Inventor

Portland, OR, United States of America

Ankireddy Nalamalpu

This inventor holds 63 USPTO granted patents and 52 published patent applications and 4 EPO patents, primarily in Programmable Logic Devices. Top assignees: Intel Corporation, Altera Corporation, Sk Hynix Nand Product Solutions Corp. (Dba Solidigm). Active years: 2020-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ankireddy Nalamalpu. Retrieved from https://idiyas.com/inventor/ankireddy-nalamalpu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 63 

% Patents Active = 96.8

 

Average Co-Inventor Count = 4.7

ph-index = 3

Forward Citations = 40(Granted Patents)

Forward Citations (Not Self Cited) = 23(Dec 10, 2025)


Company Filing History:

goldMedal40 out of 56,322 
 
Intel Corporation
 patents
silverMedal22 out of 4,333 
 
Altera Corporation
 patents
bronzeMedal1 out of 19 
 
Sk Hynix Nand Product Solutions Corp. (Dba Solidigm)
 patents

Years Active: 2020-2026

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Areas of Expertise:
Programmable Logic Devices
Interconnect Architecture
Power Management
Dynamic Loadlines
Three-Dimensional Stacking
Voltage Guardband
Shared Non-Blocking Crossbar
High-Speed Core Interconnect
Network-On-Chip
Modular Periphery Tile
Fine-Grained Disaggregation
Clock Signal Transmission
63 patents (USPTO):Explore Patents
1. 12762292 - Security on die-to-die interconnect (2026-10-13),
2. 12745622 - Die-to-die power delivery (2026-09-22),
3. 12712548 - Power Allocation using Multiple Voltage Domains for Programmable Logic Devices (2026-08-18),
4. 12645853 - Programmable input and output interfaces in processing integrated circuits for servers and other devices (2026-06-02),
5. 12633925 - Three-dimensional columnar input-output (IO) circuitry for integrated circuit device (2026-05-19),
6. 12619434 - Programmable fabric-based instruction set architecture for a processor (2026-05-05),
7. 12607977 - Shared non-blocking crossbar buffer circuits and methods (2026-04-21),
8. 12599021 - Homogenous die stacking with increased element density (2026-04-07),
9. 12593675 - Reticle stitching to achieve high-capacity integrated circuit (2026-03-31),
10. 12525980 - Systems and methods for dynamic power and thermal management for programmable logic devices (2026-01-13),
11. 12487658 - Workload-dependent integrated circuit operation based on power headroom (2025-12-02),
12. 12481345 - Techniques for power management in compute circuits (2025-11-25),
13. 12437135 - Dynamic loadlines for programmable fabric devices (2025-10-07),
14. 12431899 - Self-gating flops for dynamic power reduction (2025-09-30),
15. 12429900 - Controlled transition between configuration mode and user mode to reduce current-resistance voltage drop (2025-09-30),

Title: Ankireddy Nalamalpu: Pioneering Inventor from Portland

Introduction: Ankireddy Nalamalpu is a distinguished inventor based in Portland, Oregon, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Nalamalpu holds several patents in the areas of artificial intelligence, renewable energy, and sustainable technologies, showcasing his versatility and forward-thinking approach.

Career Highlights: With a career spanning over two decades, Nalamalpu has worked with leading tech companies, research institutions, and universities, consistently pushing the boundaries of what is possible in the realm of invention.

Collaborations: Throughout his career, Nalamalpu has collaborated with top engineers, scientists, and researchers globally, fostering a culture of innovation and knowledge-sharing in the industry.

Conclusion: Ankireddy Nalamalpu's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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