The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Sep. 30, 2022
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Atul Maheshwari, Portland, OR (US);

Mahesh K. Kumashikar, Bangalore, IN;

Ankireddy Nalamalpu, Portland, OR (US);

MD Altaf Hossain, Portland, OR (US);

Mahesh A. Iyer, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17736 (2020.01); H10W 20/43 (2026.01);
U.S. Cl.
CPC ...
H03K 19/1774 (2013.01); H10W 20/43 (2026.01);
Abstract

A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.


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Maheshwari, Atul. (2026). Backside metallization for fpga resources (U.S. Patent No. 12785692). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12785692

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