The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2025
Filed:
Dec. 22, 2021
Intel Corporation, Santa Clara, CA (US);
Yuet Li, Fremont, CA (US);
Ankireddy Nalamalpu, Portland, OR (US);
Atul Maheshwari, Portland, OR (US);
Md Altaf Hossain, Portland, OR (US);
Mahesh K. Kumashikar, Bangalore, IN;
Mahesh A. Iyer, Fremont, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Systems or methods of the present disclosure may provide for determining a loadline for operation of a programmable logic fabric where the loadline is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The loadline may be determined using software modeling for the design or configuration. Additionally or alternatively, the loadline may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.