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Dheeraj R Subbareddy

This inventor holds 63 USPTO granted patents and 18 published patent applications and 6 EPO patents, primarily in Programmable Logic Devices. Top assignees: Intel Corporation, Altera Corporation. Active years: 2016-2026.

USPTO Granted Patents = 63 (Patent Applications = 18)

% Patents Active = 95.2

EPO Patents = 6 (Patent Applications = 10)

Average Co-Inventor Count = 5.3

ph-index = 4

Forward Citations = 72(Granted Patents)

Forward Citations (Not Self Cited) = 57(Dec 10, 2025)

Location History:

Hillsboro, OR (US) (2016 - 2019)
Santa Clara, CA (US) (2021 - 2023)
Portland, OR (US) (2019 - 2024)

Company Filing History:

Years Active: 2016-2026

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Areas of Expertise:

Programmable Logic

Interconnect Architecture

Microelectronics

Die Stacking

Network-On-Chip

Power Management

Clock Signal Transmission

Flexible Data Width

Modular Periphery Tile

Three-Dimensional Stacking

Silicon Interposer

Dynamic Timing Modeling

63 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12619434 - Programmable fabric-based instruction set architecture for a processor (2026-05-05),

2. 12599021 - Homogenous die stacking with increased element density (2026-04-07),

3. 12422477 - Segmented row repair for programmable logic devices (2025-09-23),

4. 12355359 - Switch based on load current (2025-07-08),

5. 12353238 - Flexible instruction set architecture supporting varying frequencies (2025-07-08),

6. 12347783 - Interconnect architecture with silicon interposer and EMIB (2025-07-01),

7. 12341511 - Power management using voltage islands on programmable logic devices (2025-06-24),

8. 12334449 - Selective use of different advanced interface bus with electronic chips (2025-06-17),

9. 12294368 - Three-dimensional stacked programmable logic fabric and processor design architecture (2025-05-06),

10. 12273107 - Dynamically scalable timing and power models for programmable logic devices (2025-04-08),

11. 12266625 - Innovative interconnect design for package architecture to improve latency (2025-04-01),

12. 12237831 - Network-on-chip (NOC) with flexible data width (2025-02-25),

13. 12216150 - On-die aging measurements for dynamic timing modeling (2025-02-04),

14. 12206410 - Programmable logic device with fine-grained disaggregation (2025-01-21),

15. 12153866 - Modular periphery tile for integrated circuit device (2024-11-26),

Title: Innovator Spotlight: Dheeraj R. Subbareddy

Introduction:

Meet Dheeraj R. Subbareddy, a prolific inventor based in Hillsboro, OR, United States, who has made significant contributions to the field of microelectronics. With an impressive portfolio of 45 patents, Dheeraj is known for his innovative approach to integrated circuit design.

Latest Patents:

Dheeraj's recent patents showcase his expertise in improving package architecture to enhance circuit performance. One notable invention involves an innovative interconnect design that reduces latency in signal transmission between dies, thereby boosting circuit operating speed. Another patent introduces a unique cooling arrangement for stacked integrated circuit packages, enabling efficient heat transfer between components.

Career Highlights:

Dheeraj R. Subbareddy is a valuable asset to Intel Corporation, where he channels his expertise in microelectronics to drive innovation and technological advancement. His contributions to the company's intellectual property portfolio have cemented his reputation as a visionary inventor in the field.

Collaborations:

In his professional journey, Dheeraj has collaborated with esteemed colleagues such as Ankireddy Nalamalpu and MD Altaf Hossain. Through teamwork and shared expertise, these individuals have collectively contributed to groundbreaking advancements in integrated circuit technology.

Conclusion:

In conclusion, Dheeraj R. Subbareddy's relentless pursuit of innovation and his commitment to pushing the boundaries of microelectronics have established him as a leading figure in the industry. His groundbreaking patents and collaborative spirit continue to shape the landscape of integrated circuit design, inspiring future generations of inventors.

Profile summary based on public USPTO records.

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