Intel Corporation

Altera Corporation

Dheeraj R Subbareddy

Ankireddy Nalamalpu

Md Altaf Hossain

Lai Guan Tang

Mahesh K Kumashikar

Robert L Sankman

Sean R Atsatt

Chee Hak Teh

Eugene Gorbatov

David A Koufaty

Eliezer Weissmann

Alon Naveh

Ravindranath Vithal Mahajan

Ganapati Srinivasa

Scott D Hahn

Paolo L Narvaez

Mahesh A Iyer

Atul Maheshwari

Mishali Naik

Kavitha Prasad

Paul Brett

Sharath Raghava

Harsha Gupta

Abirami Prabhakaran

Andrew J Herdrich

Inder M Sodhi

Russell Jerome Fenger

Gaurav Khanna

Krishnakanth Venkata Sistla

Gregg William Baeckler

Ankush Varma

Yen-Cheng Liu

Gerald S Pasdast

George Zacharias Chrysos

Vedaraman Geetha

Sandeep B Sane

James Loran Ball

Andrew D Henroid

Jeffrey D Chamberlain

Anshuman Thakur

William R Halleck

Nevine Nassif

Tejpal Singh

Srikanth Nimmagadda

Siva Soumya Eachempati

Carleton L Molnar

John R Ayers

Debendra Mallik

Rajat Agarwal

Ravi Prakash Gutala

Scott J Weber

Michael Mishaeli

Ram S Viswanath

Aravind Raghavendra Dasu

Sriram Srinivasan

Bret L Toll

Jason W Brandt

Ravishankar Iyer

Sanjay Kumar

Stephen Anthony Fischer

Ashish V Choubal

Hisham Shafi

Rinat Rappoport

Chooi Pei Lim

Nagabhushan Chitlur

Jeffrey Chromczak

Oron Lenz

Yuet Li

Sanjeev S Sahagirdar

Dhananjay Raghavan

Efraim Rotem

Rajesh M Sankaran

Reshma Lal

Dinesh Somasekhar

Andrew V Anderson

Ronny Ronen

Boris Ginzburg

Bin Xing

Bryant E Bigbee

Anil Aggarwal

Aamer Jaleel

Rahul Pal

Yuval Yosef

Subramanya R Dulloor

Jeffrey R Jackson

Tong Li

Hisham Abu-Salah

Arun Jangity

Dheemanth Nagaraj

Ilya Osadchiy

Daniel S Klowden

Kemal Aygün

Kenzo Van Craeynest

Russel J Fenger

Guarav Khanna

Avi Mendleson

Casey Thielen

Ramya Yeluri

Ian Kuon

Rajesh Vivekanandham

Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.

Segmented row repair for programmable logic devices

A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Systems and methods for transitioning data between the programmable fabric and the processor associated with different clock domains is described.

Flexible instruction set architecture supporting varying frequencies

Systems or methods of the present disclosure may provide for operating a programmable fabric including multiple programmable elements organized into a number of power domains that utilize a common voltage within the respective power domains. A current sensor senses a current of the programmable fabric. When the sensed current has crossed a threshold, the programmable fabric changes the number of power domains.

Switch based on load current

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Interconnect architecture with silicon interposer and EMIB

Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.

Power management using voltage islands on programmable logic devices

A digitally communicative circuit may use standardized interfaces for connection and communication with other circuit components. Such digitally communicative circuit may benefit from using wider variety of interconnect schemes with the respective interfaces for transmission and reception of data. Some chiplets may communicate using a high data bandwidth interface while other chiplets may communicate using interfaces with lower data bandwidth. Alternate interface is introduced that may facilitate scaled communication with Advanced Interface Bus 2.0 without translation circuitry and with different data bandwidth.

Selective use of different advanced interface bus with electronic chips

The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

Three-dimensional stacked programmable logic fabric and processor design architecture

Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

Dynamically scalable timing and power models for programmable logic devices

An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

Innovative interconnect design for package architecture to improve latency

Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Network-on-chip (NOC) with flexible data width

A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

On-die aging measurements for dynamic timing modeling

A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

Programmable logic device with fine-grained disaggregation

Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Modular periphery tile for integrated circuit device

An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.

Techniques for clock signal transmission in integrated circuits and interposers

A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

Low-latency optical connection for CXL for a server CPU

Growing community of inventors

Hillsboro, OR, United States of America

Dheeraj R Subbareddy