IDiyas

For the Inventor, By the Inventor

San Jose, CA, United States of America

Kavitha Prasad

USPTO Granted Patents = 12 

 

Average Co-Inventor Count = 4.8

ph-index = 3

Forward Citations = 38(Granted Patents)


Company Filing History:

goldMedal9 out of 54,664 
 
Intel Corporation
 patents
silverMedal3 out of 18 
 
Sima Technologies, Inc.
 patents

Years Active: 2004-2025

where 'Filed Patents' based on already Granted Patents

12 patents (USPTO):
1. 12237831 - Network-on-chip (NOC) with flexible data width (2025-02-25),
2. 11789883 - Inter-die communication of programmable logic devices (2023-10-17),
3. 11700002 - Network-on-chip (NOC) with flexible data width (2023-07-11),
4. 11403519 - Machine learning network implemented by statically scheduled instructions, with system-on-chip (2022-08-02),
5. 11354570 - Machine learning network implemented by statically scheduled instructions, with MLA chip (2022-06-07),
6. 11342918 - Network-on-chip (NOC) with flexible data width (2022-05-24),
7. 11321607 - Machine learning network implemented by statically scheduled instructions, with compiler (2022-05-03),
8. 10790827 - Network-on-chip (NOC) with flexible data width (2020-09-29),
9. 10649927 - Dual in-line memory module (DIMM) programmable accelerator card (2020-05-12),
10. 7567566 - Method and apparatus to perform aging (2009-07-28),
11. 7152140 - Masking parity information associated with a ternary content addressable memory (2006-12-19),
12. 6801143 - Method and apparatus for generating gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO'S (2004-10-05),

Title: Kavitha Prasad: Innovator in Network-on-Chip Technologies

Introduction

Kavitha Prasad is a prominent inventor based in San Jose, California, known for her significant contributions to the field of integrated circuit design. With a total of 12 patents to her name, she has made remarkable advancements in network-on-chip (NOC) technologies.

Latest Patents

One of her latest patents focuses on a Network-on-Chip (NOC) with flexible data width. The techniques described in this patent relate to providing a programmable interconnect network. This method includes determining a transmission parameter, bonding one or more channels of an interconnect network based on the transmission parameter, and power-gating any unused channels after the bonding. Another notable patent involves inter-die communication of programmable logic devices. This integrated circuit device includes a first network on chip (NOC) circuit configured to receive a set of data and transfer it to a first node of the first NOC circuitry. The first node is designed to transfer the data to a second NOC circuit of an additional integrated circuit device that is separate from the original device.

Career Highlights

Kavitha has worked with leading technology companies, including Intel Corporation and Sima Technologies, Inc. Her experience in these organizations has allowed her to refine her skills and contribute to groundbreaking projects in the semiconductor industry.

Collaborations

Throughout her career, Kavitha has collaborated with talented individuals such as Sharath Raghava and Dheeraj R Subbareddy. These partnerships have fostered innovation and have been instrumental in her success as an inventor.

Conclusion

Kavitha Prasad stands out as a leading figure in the realm of network-on-chip technologies. Her innovative patents and collaborations reflect her dedication to advancing the field of integrated circuits.

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