Intel Corporation

Sima Technologies, Inc.

Kavitha Prasad

Dheeraj R Subbareddy

Ankireddy Nalamalpu

Harsha Gupta

Sharath Raghava

Sean R Atsatt

James Loran Ball

Nishit Harshad Shah

Srivathsa Dhruvanarayan

Reed Kotler

Spenser Don Gilliland

Yogesh Laxmikant Chobe

Moenes Zaher Iskarous

Sedny S J Attia

Miguel A Guerrero

Sreenath Kurupati

Bradley L Taylor

Kin Yip Sit

Ashwani Oberai

Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Network-on-chip (NOC) with flexible data width

An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

Inter-die communication of programmable logic devices

A compiler receives a description of a machine learning network and generates a computer program that implements the machine learning network. The computer program includes statically scheduled instructions that are executed by a mesh of processing elements (Tiles). The instructions executed by the Tiles are statically scheduled because the compiler can determine which instructions are executed by which Tiles at what times. For example, for the statically scheduled instructions, there are no conditions, branching or data dependencies that can be resolved only at run-time, and which would affect the timing and order of the execution of the instructions.

Machine learning network implemented by statically scheduled instructions, with system-on-chip

Machine learning network implemented by statically scheduled instructions, with MLA chip

Machine learning network implemented by statically scheduled instructions, with compiler

A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.

Dual in-line memory module (DIMM) programmable accelerator card

A method and apparatus to perform aging are described. A method to perform timing comprises receiving an address and retrieving an age zone value associated with the received address. A time is then determined using the retrieved age zone value. The determined time may then be associated with the received address.

Method and apparatus to perform aging

According to some embodiments, a parity check is provided for ternary content addressable memory. For example, it may be arranged for a read request to be transmitted to a ternary content addressable memory unit. Data content may then be received from the memory unit in response to the read request, a parity check may be performed on the data content. According to some embodiments, parity information may be masked when the memory unit is queried.

Masking parity information associated with a ternary content addressable memory

A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

Method and apparatus for generating gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO'S

Growing community of inventors

San Jose, CA, United States of America

Kavitha Prasad