The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2022
Filed:
Dec. 27, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sean R. Atsatt, Santa Cruz, CA (US);
Scott J. Weber, Piedmont, CA (US);
Aravind Raghavendra Dasu, Milpitas, CA (US);
Ravi Prakash Gutala, San Jose, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 15/02 (2006.01); G06F 1/20 (2006.01); H03K 19/0175 (2006.01); H03K 19/003 (2006.01); H03K 19/00 (2006.01); G06F 1/3287 (2019.01); H01L 23/538 (2006.01); G06F 1/3296 (2019.01); H01L 25/18 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 23/34 (2006.01);
U.S. Cl.
CPC ...
G06F 1/206 (2013.01); G05B 15/02 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); H01L 23/5383 (2013.01); H03K 19/0008 (2013.01); H03K 19/00369 (2013.01); H03K 19/017581 (2013.01); H01L 23/34 (2013.01); H01L 23/367 (2013.01); H01L 23/3675 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1435 (2013.01);
Abstract
An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.