The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Apr. 04, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Sean Atsatt, Santa Cruz, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17736 (2020.01); G11C 15/00 (2006.01); H01L 25/18 (2023.01); H03K 19/173 (2006.01); H03K 19/17728 (2020.01); H03K 19/17756 (2020.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17736 (2013.01); G11C 15/00 (2013.01); H01L 25/18 (2013.01); H03K 19/1737 (2013.01); H03K 19/17728 (2013.01); H03K 19/17756 (2013.01); H03K 19/1776 (2013.01);
Abstract

Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.


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