The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Aug. 02, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chee Hak Teh, Bayan Lepas, MY;

Ankireddy Nalamalpu, Portland, OR (US);

Md Altaf Hossain, Portland, OR (US);

Dheeraj Subbareddy, Portland, OR (US);

Sean R. Atsatt, Santa Cruz, CA (US);

Lai Guan Tang, Tanjung Bungah, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/34 (2020.01); H03K 19/17736 (2020.01); H04L 12/43 (2006.01); G06F 15/78 (2006.01); H03K 19/17796 (2020.01);
U.S. Cl.
CPC ...
G06F 30/34 (2020.01); G06F 15/7825 (2013.01); H03K 19/17744 (2013.01); H03K 19/17796 (2013.01); H04L 12/43 (2013.01);
Abstract

Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.


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