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For the Inventor, By the Inventor

Tokyo, Japan

Sadaaki Masuoka

This inventor holds 14 USPTO granted patents. Top assignees: Nec Corporation, Nec Electronics Corporation. Active years: 1998-2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sadaaki Masuoka. Retrieved from https://idiyas.com/inventor/sadaaki-masuoka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 78.6

Average Co-Inventor Count = 1.2

ph-index = 7

Forward Citations = 182(Granted Patents)


Location History:

  • Tokyo, JP (1998 - 2004)
  • Kawasaki, JP (2007 - 2009)

Company Filing History:

goldMedal8 out of 36,684 
 
Nec Corporation
 patents
silverMedal6 out of 2,467 
 
Nec Electronics Corporation
 patents

Years Active: 1998-2009

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14 patents (USPTO):Explore Patents
1. 7498626 - Semiconductor device and method of manufacturing the same (2009-03-03),
2. 7256462 - Semiconductor device (2007-08-14),
3. 7190009 - Semiconductor device (2007-03-13),
4. 6798027 - Semiconductor device including gate insulation films having different thicknesses (2004-09-28),
5. 6627490 - Semiconductor device and method for fabricating the same (2003-09-30),
6. 6551884 - Semiconductor device including gate insulation films having different thicknesses (2003-04-22),
7. 6472714 - Semiconductor device in which memory cells and peripheral circuits are provided on the same circuit (2002-10-29),
8. 6413811 - Method of forming a shared contact in a semiconductor device including MOSFETS (2002-07-02),
9. 6342413 - Method of manufacturing semiconductor device (2002-01-29),
10. 6217357 - Method of manufacturing two-power supply voltage compatible CMOS semiconductor device (2001-04-17),
11. 6133082 - Method of fabricating CMOS semiconductor device (2000-10-17),
12. 5994743 - Semiconductor device having different sidewall widths and different (1999-11-30),
13. 5994179 - Method of fabricating a MOSFET featuring an effective suppression of (1999-11-30),
14. 5733792 - MOS field effect transistor with improved pocket regions for suppressing (1998-03-31),

Title: Sadaaki Masuoka: Innovator in Semiconductor Technology

Introduction

Sadaaki Masuoka is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 14 patents. His work has paved the way for advancements in semiconductor devices, enhancing their performance and reliability.

Latest Patents

Masuoka's latest patents include innovative designs for semiconductor devices. One notable invention is a semiconductor device that features a capacitive element with a very uniform capacitive value. This invention also outlines a method for manufacturing the semiconductor device, which includes forming an N-type well and a conductive layer on a P-type semiconductor substrate. Another significant patent focuses on providing a high-quality semiconductor device that allows for independent control of threshold voltage values of gate electrodes in transistors. This device comprises a P-type silicon substrate and multiple P-type wells connected via the substrate's bottom surface, surrounded by an N-type well.

Career Highlights

Throughout his career, Sadaaki Masuoka has worked with notable companies such as NEC Corporation and NEC Electronics Corporation. His experience in these organizations has contributed to his expertise in semiconductor technology and innovation.

Collaborations

Masuoka has collaborated with several talented individuals in the field, including Kiyotaka Imai and Hiroaki Ohkubo. These collaborations have further enriched his work and led to advancements in semiconductor devices.

Conclusion

Sadaaki Masuoka's contributions to semiconductor technology are invaluable. His innovative patents and collaborations have significantly impacted the industry, showcasing his expertise and dedication to advancing technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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