The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2002

Filed:

Oct. 23, 2000
Applicant:
Inventors:

Sadaaki Masuoka, Tokyo, JP;

Kiyotaka Imai, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ; H01L 2/18234 ;
U.S. Cl.
CPC ...
H01L 2/1336 ; H01L 2/18234 ;
Abstract

In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask ( ), wells ( ) and first threshold adjustment regions ( ) are formed at transistor areas ( n, n) for the second and the third MOS transistors in a semiconductor substrate ( ). Next, using a second mask ( ), second threshold adjustment regions ( ) are formed at transistor areas ( n and n) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.


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