The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 1999
Filed:
Jun. 03, 1997
Sadaaki Masuoka, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
In order to suppress a reverse short-channel effect, a plurality of dummy gates, wherein gate electrodes are respectively to be formed, are formed in selective regions on the substrate. Further, the regions wherein first conductive type elements are to be formed are masked. Thereafter, a first conductive type well by ion planting a first conductive type impurity is formed. Further, a second conductive type source and drain region is formed by ion planting a second conductive type impurity. The resist covering the regions, wherein the first conductive type elements are to be formed, are removed. Following this, regions wherein second conductive type elements are to be formed, are masked by a resist. Further, a second conductive type well is formed by ion planting a second conductive type impurity. A first conductive type source and drain region is formed by ion planting a first conductive type impurity. Subsequently, the resist covering the regions wherein the second conductive type elements are to be formed, is removed, after which the source and drain regions are activated. Thereafter, a first layer on the substrate is formed, and the first layer is polished until the surface of each of the dummy gates is exposed. Then, the dummy gates are removed and, regions wherein the first conductive type elements are to be formed are masked. After a first conductive type impurity is implanted, the resist covering the regions wherein the first conductive type elements are to be formed is removed. Further, regions wherein the second conductive type elements are to be formed, are masked. Then, a second conductive type impurity is implanted, after which the resist covering the regions wherein the second conductive type elements are to be formed is removed. Further, a gate oxide layer in each recess is left by removing the dummy gate. Following this, after the substrate is covered with a gate electrode material, the gate electrode material covering the substrate is polished until the first layer is exposed.