Hsinchu, Taiwan

Ruey-Hsin Liu

This inventor holds 161 USPTO granted patents and 22 published patent applications, primarily in Semiconductor Devices (CPC class H01L29-402). Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2000-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ruey-Hsin Liu. Retrieved from https://idiyas.com/inventor/ruey-hsin-liu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 161 

% Patents Active = 77.6

Average Co-Inventor Count = 4.0

ph-index = 10

Forward Citations = 559(Granted Patents)

Forward Citations (Not Self Cited) = 490(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Miaoli, TW (2005 - 2009)
  • Hsin-Chu, TW (2000 - 2024)
  • Hsinchu, TW (2024)

Company Filing History:


Years Active: 2000-2026

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Areas of Expertise:
High Voltage Device
Semiconductor Isolation
Power MOSFET
Noise Reduction
Transistor Device
Triple Well Diode
Avalanche-Protected Transistors
Integrated Circuit
Field Plate Design
Layout Optimization
Vertical Power MOS
Selective Polysilicon Doping
161 patents (USPTO):Explore Patents

Title: Ruey-Hsin Liu: Driving Innovation in Semiconductor Technology

Introduction:

Ruey-Hsin Liu, an esteemed innovator hailing from Hsin-Chu, Taiwan, has made significant contributions in the fields of electronics, telecommunications, and semiconductor technology. With an impressive 149 patents to his name, Liu's inventive thinking has been instrumental in shaping advancements in these industries. This article explores his latest patents, career highlights, and collaborations, highlighting his remarkable impact in the global innovation landscape.

Latest Patents:

Liu's recent patents demonstrate his expertise in semiconductor device design and optimization:

1. Layout to reduce noise in semiconductor devices:

This patent presents a novel layout for a semiconductor device aiming to reduce noise interference. By strategically placing the isolation structure and utilizing silicide blocking structures, noise levels can be minimized, enhancing the overall performance of the device.

2. Semiconductor device having multiple wells and method of making:

This patent introduces a semiconductor device with multiple wells for improved functionality. By incorporating different dopant types and precise well arrangements, performance enhancements and efficient circuit operations are achieved.

Career Highlights:

Throughout his illustrious career, Ruey-Hsin Liu has achieved numerous milestones and garnered recognition for his exceptional work. Considered a trailblazer in his field, his contributions have had a profound impact on the semiconductor industry. Some notable highlights include:

1. Taiwan Semiconductor Manufacturing Company (TSMC):

Liu is currently associated with TSMC, one of the world's leading semiconductor foundries. His work at TSMC has been instrumental in the company's technological advancements and market dominance.

Collaborations:

Liu's commitment to innovation has often led him to collaborate with other esteemed professionals. Notably, two of his influential colleagues are Chih-Chang Cheng and Hsueh-Liang Chou. Their combined expertise has resulted in groundbreaking developments within semiconductor technology and related fields.

Conclusion:

Ruey-Hsin Liu's contributions to the electronics, telecommunications, and semiconductor industries have solidified his position as a respected figure in the field of innovation. With an impressive patent portfolio and significant career achievements, he continues to propel advancements in semiconductor device design. Collaborations with talented colleagues further amplify his impact, shaping the industry's future. Ruey-Hsin Liu's groundbreaking ideas and dedication to his craft inspire others and set a high bar for innovation in the global marketplace.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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