The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2024
Filed:
Jul. 27, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Chen-Liang Chu, Hsin-Chu, TW;
Chien-Chih Chou, New Taipei, TW;
Chih-Chang Cheng, Hsinchu, TW;
Yi-Huan Chen, Hsin Chu, TW;
Kong-Beng Thei, Pao-Shan Village, TW;
Ming-Ta Lei, Hsin-Chu, TW;
Ruey-Hsin Liu, Hsin-Chu, TW;
Ta-Yuan Kung, New Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.