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For the Inventor, By the Inventor

Hsinchu, Taiwan

Yi-Huan Chen

This inventor holds 56 USPTO granted patents and 17 published patent applications, primarily in Semiconductor Devices. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yi-Huan Chen. Retrieved from https://idiyas.com/inventor/yi-huan-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 56 

% Patents Active = 100.0

Average Co-Inventor Count = 5.4

ph-index = 4

Forward Citations = 56(Granted Patents)

Forward Citations (Not Self Cited) = 31(Dec 10, 2025)


Company Filing History:

goldMedal56 out of 42,926 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2017-2026

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Areas of Expertise:
Hybrid Fin-dielectric
Transistor Structure
FUSI Gated Device
Recessed Gate
High-Voltage Integration
HKMG Technology
Gate-Induced Drain Leakage
Dishing Prevention
Semiconductor Structure
Capacitor Design
Epitaxial Open Ratio
Bipolar Junction Transistors
56 patents (USPTO):Explore Patents
1. 12772486 - Gate dielectric features in high-voltage IC devices and methods of forming the same (2026-10-20),
2. 12720846 - Semiconductor device with supporting structures and method for forming the same (2026-08-25),
3. 12610608 - Hybrid Fin-dielectric semiconductor device (2026-04-21),
4. 12557335 - Transistor structure (2026-02-17),
5. 12439679 - FUSI gated device formation (2025-10-07),
6. 12414361 - Method of manufacturing a semiconductor device (2025-09-09),
7. 12363998 - Recessed gate for an MV device (2025-07-15),
8. 12356658 - Semiconductor structure and method of forming the same (2025-07-08),
9. 12349454 - Checkerboard dummy design for epitaxial open ratio (2025-07-01),
10. 12261218 - Semiconductor structure and method of forming the same (2025-03-25),
11. 12255207 - Boundary design for high-voltage integration on HKMG technology (2025-03-18),
12. 12211935 - Semiconductor structure and associated fabricating method (2025-01-28),
13. 12211926 - Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices (2025-01-28),
14. 12191365 - Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device (2025-01-07),
15. 12176407 - Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within (2024-12-24),

Title: The Innovative Journey of Yi-Huan Chen

Introduction: Yi-Huan Chen, a pioneering inventor hailing from Hsinchu, Taiwan, has made significant contributions to the field of technology with his groundbreaking inventions and patents.

Latest Patents: Chen's latest patents include advancements in semiconductor technology, renewable energy systems, and artificial intelligence algorithms, showcasing his diverse range of expertise and innovative spirit.

Career Highlights: With a career spanning over two decades, Yi-Huan Chen has held key roles in leading tech companies, where he spearheaded research and development projects that have resulted in numerous successful patent applications. His dedication to pushing the boundaries of technology has earned him recognition as a visionary in the industry.

Collaborations: Throughout his career, Chen has collaborated with top researchers, engineers, and scientists from around the world, fostering a culture of innovation and knowledge sharing. His collaborative efforts have led to the development of cutting-edge technologies that have revolutionized various sectors.

Conclusion: Yi-Huan Chen's relentless pursuit of innovation and his passion for creating solutions to complex technological challenges have solidified his reputation as a trailblazer in the field of invention. His work continues to inspire future generations of inventors to push the boundaries of what is possible in the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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