The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Aug. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yi-Huan Chen, Hsin Chu, TW;

Chien-Chih Chou, New Taipei, TW;

Ta-Wei Lin, Minxiong Township, TW;

Hsiao-Chin Tuan, Taowan, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Kong-Beng Thei, Pao-Shan Village, TW;

Chia-Hong Wu, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/28 (2025.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H10D 30/01 (2025.01); H10D 62/13 (2025.01); H10D 64/27 (2025.01); H10D 64/62 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/28088 (2013.01); H01L 21/31053 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H10D 30/0212 (2025.01); H10D 30/0215 (2025.01); H10D 62/151 (2025.01); H10D 64/517 (2025.01); H10D 64/62 (2025.01); H10D 64/667 (2025.01); H10D 64/685 (2025.01); H10D 84/017 (2025.01); H10D 84/0174 (2025.01); H10D 84/0186 (2025.01); H10D 84/85 (2025.01); H10D 64/514 (2025.01); H10D 64/691 (2025.01);
Abstract

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a stack of gate layers over a substrate. The stack of gate layers includes a first dielectric layer on the substrate, a conductive layer on the first dielectric layer, and a polysilicon layer on the conductive layer. A pair of source/drain regions is formed on opposing sides of a central region of the polysilicon layer. The central portion of the polysilicon layer is converted to a first silicide layer. The first silicide layer is spaced between inner sidewalls of the polysilicon layer.


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