Gate dielectric features in high-voltage ic devices and methods of forming the same

Abstract

Some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. The integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a perimeter portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.