The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2024
Filed:
Jan. 05, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Po-Chih Su, New Taipei, TW;
Ruey-Hsin Liu, Hsin-Chu, TW;
Pei-Lun Wang, Hsinchu County, TW;
Jia-Rui Lee, Kaohsiung, TW;
Jyun-Guan Jhou, Taoyuan, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7835 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/4991 (2013.01); H01L 29/66484 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66659 (2013.01); H01L 29/7831 (2013.01);
Abstract
The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.