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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Rochit Rajsuman

This inventor holds 23 USPTO granted patents, primarily in Semiconductor Testing. Top assignee: Adv Antest Corporation. Active years: 2001-2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rochit Rajsuman. Retrieved from https://idiyas.com/inventor/rochit-rajsuman

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 23

% Patents Active = 56.5

Average Co-Inventor Count = 2.2

ph-index = 13

Forward Citations = 558(Granted Patents)


Company Filing History:

goldMedal23 out of 2,281 
 
Adv Antest Corporation
 patents

Years Active: 2001-2007

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Areas of Expertise:
Integrated Circuits
ASIC
SoC
Test Systems
Validation Methods
Calibration Techniques
Memory Testing
Debugging
Performance Validation
Analog Cores
Glitch Detection
Embedded Systems
23 patents (USPTO):Explore Patents
1. 7194668 - Event based test method for debugging timing related failures in integrated circuits (2007-03-20),
2. 7178115 - Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing (2007-02-13),
3. 7089517 - Method for design validation of complex IC (2006-08-08),
4. 7089135 - Event based IC test system (2006-08-08),
5. 6948105 - Method of evaluating core based system-on-a-chip (SoC) and structure of SoC incorporating same (2005-09-20),
6. 6944808 - Method of evaluating core based system-on-a-chip (2005-09-13),
7. 6915469 - High speed vector access method from pattern memory for test systems (2005-07-05),
8. 6804620 - Calibration method for system performance validation of automatic test equipment (2004-10-12),
9. 6791316 - High speed semiconductor test system using radially arranged pin cards (2004-09-14),
10. 6747447 - Locking apparatus and loadboard assembly (2004-06-08),
11. 6678645 - Method and apparatus for SoC design validation (2004-01-13),
12. 6651204 - Modular architecture for memory testing on event based test system (2003-11-18),
13. 6629282 - Module based flexible semiconductor test system (2003-09-30),
14. 6594609 - Scan vector support for event based test system (2003-07-15),
15. 6578169 - Data failure memory compaction for semiconductor test system (2003-06-10),

Title: Rochit Rajsuman - Innovator from Santa Clara, CA

Introduction: Rochit Rajsuman is a prolific inventor based in Santa Clara, CA, known for his groundbreaking contributions to various technological fields.

Latest Patents: Rochit Rajsuman holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies.

Career Highlights: With a career spanning over two decades, Rochit Rajsuman has worked with leading tech companies, research institutions, and universities to develop cutting-edge solutions that have had a significant impact on the industry.

Collaborations: Throughout his career, Rochit Rajsuman has collaborated with top engineers, scientists, and innovators to push the boundaries of innovation and bring revolutionary ideas to life.

Conclusion: Rochit Rajsuman's dedication to innovation and his passion for creating solutions to complex challenges make him a standout figure in the world of technology and invention.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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