The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2007

Filed:

Apr. 11, 2003
Applicants:

Ankan Pramanick, Santa Clara, CA (US);

Siddharth Sawe, Santa Clara, CA (US);

Rochit Rajsuman, Santa Clara, CA (US);

Inventors:

Ankan Pramanick, Santa Clara, CA (US);

Siddharth Sawe, Santa Clara, CA (US);

Rochit Rajsuman, Santa Clara, CA (US);

Assignee:

Advantest Corp., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06K 5/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A test method for debugging failures of an IC device with use of an event based semiconductor test system is capable of distinguishing a timing related failure from other failures. The test method includes the steps of: applying a test signal to a DUT and evaluating a response output of the DUT, detecting a failure in the response output, identifying a reference clock signal related to the failure, identifying a portion of the reference clock signal that is directly related to the failure, and incrementally changing a timing of events for the identified portion of the reference clock signal to detect change in the response output from the DUT.


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