Adv Antest Corporation

Rochit Rajsuman

Hiroaki Yamoto

Shigeru Sugamori

Anthony Le

James Alan Turnquist

Robert F Sauer

Ankan Pramanick

Douglas Vincent Larson

Niels Markert

Hiroki Yamoto

Bruce R Parnas

Carol Qiao Tong

Siddharth Sawe

A test method for debugging failures of an IC device with use of an event based semiconductor test system is capable of distinguishing a timing related failure from other failures. The test method includes the steps of: applying a test signal to a DUT and evaluating a response output of the DUT, detecting a failure in the response output, identifying a reference clock signal related to the failure, identifying a portion of the reference clock signal that is directly related to the failure, and incrementally changing a timing of events for the identified portion of the reference clock signal to detect change in the response output from the DUT.

Event based test method for debugging timing related failures in integrated circuits

A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logic simulation is performed on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation. Then, simulation data files are verified with use of the design data and the testbench by operating an event tester simulator, and a prototype LSI is produced through a fabrication provider by using the design data. The prototype LSI is tested by an event tester by using the test vector file and the simulation data files and test results is feedbacked to the EDA environment or the fabrication provider.

Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing

An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Event based IC test system

A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.

Method for design validation of complex IC

A method of debugging an individual core in core based system-on-a-chip (SOC) ICs with high accuracy and observability, and a structure of SOC incorporating the method. The method includes the steps of building two or more metal layers of a pad frame for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby exposing all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, and applying test vector to each core through the I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the I/O pads on the top metal layer.

Method of evaluating core based system-on-a-chip (SoC) and structure of SoC incorporating same

A method of evaluating a core based SoC detects and localizes faults in the cores or interconnects between the cores with high accuracy and observability. The method includes the steps of building two or more metal layers to create core I/O pads having all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, testing the SoC as a whole by applying test vectors to the SoC through chip I/O pads and evaluating response outputs of the SoC, testing each core in the SoC by applying core specific test vectors to the core through the core I/O pads on the top metal layer of the core and evaluating response outputs of the core, and finding a location of a fault when the fault is detected when testing the SoC chip as a whole or when testing each of the cores.

Method of evaluating core based system-on-a-chip

A method for applying test vectors to a device under test (DUT) at a speed of the DUT is disclosed. A pattern memory is re-organized into m modules, where m is a DUT/pattern memory speed ratio. Delay circuits in address lines of each module are programmed such that an address signal for a qth module is delayed by (q&#x2212;1) delay units, where each delay unit is equivalent to one DUT clock cycle. Patterns for each test are stored in these modules according to [n mod m]; where n is a number of patterns in a test. Identical addresses are simultaneously applied to the delay circuits of the m modules according to a fixed address sequence at a rate f equal to or slower than the operating frequency of the pattern memory, such that a period of f is equal to or greater than (m&#x2212;1) delay units.

High speed vector access method from pattern memory for test systems

An ATE calibration method and system that does not require external test equipment to calibrate individual functional pins and provides balanced timing skews among the functional pins and pincards is disclosed. A functional pin in the test system is selected as a reference or &ldquo;golden&rdquo; pin and another is selected as a precision measurement unit (PMU). External test equipment and the reference PMU are used to measure the AC and DC characteristics of the reference pin, and any deviation represents a measurement error in the reference PMU. All functional pins in the test system can be measured against the reference pin using the reference PMU, taking into account the measurement error, without the need for external test equipment. To ensure that skews are balanced among all pins, the location of the reference pin is selected to be as close as possible to the midpoint of the functional pin range.

Calibration method for system performance validation of automatic test equipment

A high speed semiconductor test system is so designed that pin cards in a test head are arranged in radial directions where the DUT is placed over the center of the test head. Since each of the pin cards is arranged radially, the side which faces the center is close to the DUT, and time critical components in the pin card are formed in an area close to the side of that faces the center, thereby minimizing the round-trip-delay (RTD).Moreover, each pin card is distanced equally from the DUT. Thus, the variation in the length of path connecting between the pin card and the DUT is minimized, and accordingly, the variation in RTD is also minimized.

High speed semiconductor test system using radially arranged pin cards

The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved. Based on the profile of the cam slots, the loadboard assembly can be gradually lowered to achieve contact between the printed circuit board and the contact pins on the test head and to lock the interface board.

Locking apparatus and loadboard assembly

A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The &lsqb;apparatus allows to use a&rsqb; method &lsqb;which&rsqb; includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches &lsqb;developed by an SoC designer&rsqb; and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of &lsqb;an&rsqb; the overall SoC &lsqb;and application runs&rsqb;.

Method and apparatus for SoC design validation

An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.

Modular architecture for memory testing on event based test system

A semiconductor test system for testing semiconductor devices, and particularly, to a semiconductor test system having a plurality of different types of tester modules for easily establishing different semiconductor test systems. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test head to accommodate the two or more tester modules having different performances, means provided on the test head for electrically connecting the tester modules and a device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus. One type of the performances of the tester module is high speed high timing accuracy while other type of performance is low speed low timing accuracy. Each event tester module includes a tester board which is configured as an event based tester.

Module based flexible semiconductor test system

An event based test system can generate scan vectors for testing a semiconductor device of scan design without requiring a large amount of scan memory. The test system includes an event memory for storing timing data and event type data of each event where the timing data is expressed by N data bits for defining one test vector, an event generator for generating an event with use of the timing data and the event type data, and a mode change circuit provided between the event memory and the event generator for changing signal paths between a normal mode for generating the test vectors and a scan mode for generating the scan vectors. In the test system, each bit of the N data bits in the event memory defines 2 scan vectors which are provided to the event generator in a series fashion, thereby producing the 2 scan vectors at each access of the event memory.

Scan vector support for event based test system

A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.

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Santa Clara, CA, United States of America

Rochit Rajsuman