The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2007
Filed:
Apr. 11, 2003
Rochit Rajsuman, Santa Clara, CA (US);
Hiroaki Yamoto, Santa Clara, CA (US);
Rochit Rajsuman, Santa Clara, CA (US);
Hiroaki Yamoto, Santa Clara, CA (US);
Advantest Corp., Tokyo, JP;
Abstract
A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logic simulation is performed on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation. Then, simulation data files are verified with use of the design data and the testbench by operating an event tester simulator, and a prototype LSI is produced through a fabrication provider by using the design data. The prototype LSI is tested by an event tester by using the test vector file and the simulation data files and test results is feedbacked to the EDA environment or the fabrication provider.