The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2003
Filed:
Jun. 01, 2000
Rochit Rajsuman, Santa Clara, CA (US);
Shigeru Sugamori, Santa Clara, CA (US);
Hiroaki Yamoto, Santa Clara, CA (US);
Advantest Corp., Tokyo, JP;
Abstract
An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.