Data failure memory compaction for semiconductor test system

Abstract

A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.