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For the Inventor, By the Inventor

Plano, TX, United States of America

Ping Jiang

This inventor holds 28 USPTO granted patents and 1 published patent application and 1 EPO patent, primarily in Semiconductor Fabrication. Top assignees: Texas Instruments Corporation, Tokyo Electron Limited. Active years: 2002-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ping Jiang. Retrieved from https://idiyas.com/inventor/ping-jiang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 28 

% Patents Active = 100.0

 

Average Co-Inventor Count = 3.0

ph-index = 7

Forward Citations = 249(Granted Patents)


Company Filing History:

goldMedal28 out of 29,901 
 
Texas Instruments Corporation
 patents
silverMedal1 out of 10,918 
 
Tokyo Electron Limited
 patents
where one patent can have more than one assignee

Years Active: 2002-2019

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Areas of Expertise:
Low-K Dielectric
Semiconductor Fabrication
Etch Processes
Integration Methods
Ballistic Electron Beam
Plasma Treatment
Dual Damascene
Silicided Gate
Interconnects
Stress Testing
Gas Modulation
Patterning
28 patents (USPTO):Explore Patents
1. 10453700 - Low damage low-k dielectric etch (2019-10-22),
2. 9881795 - Method of fabricating semiconductors (2018-01-30),
3. 9678132 - Capacitor combination stress testing (2017-06-13),
4. 9490143 - Method of fabricating semiconductors (2016-11-08),
5. 8083961 - Method and system for controlling the uniformity of a ballistic electron beam by RF modulation (2011-12-27),
6. 8008200 - Poison-free and low ULK damage integration scheme for damascene interconnects (2011-08-30),
7. 7943499 - FUSI integration method using SOG as a sacrificial planarization layer (2011-05-17),
8. 7884019 - Poison-free and low ULK damage integration scheme for damascene interconnects (2011-02-08),
9. 7741224 - Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics (2010-06-22),
10. 7732313 - FUSI integration method using SOG as a sacrificial planarization layer (2010-06-08),
11. 7732312 - FUSI integration method using SOG as a sacrificial planarization layer (2010-06-08),
12. 7572733 - Gas switching during an etch process to modulate the characteristics of the etch (2009-08-11),
13. 7560385 - Etching systems and processing gas specie modulation (2009-07-14),
14. 7341941 - Methods to facilitate etch uniformity and selectivity (2008-03-11),
15. 7338888 - Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same (2008-03-04),

Title: Inventor Ping Jiang - Revolutionizing Technology in Plano, TX

Introduction: Ping Jiang is a visionary inventor based in Plano, TX, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Ping Jiang holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his commitment to pushing the boundaries of technological advancement.

Career Highlights: With a career spanning over two decades, Ping Jiang has worked with leading tech companies, spearheading projects that have revolutionized industries and improved efficiency in various sectors.

Collaborations: Throughout his career, Ping Jiang has collaborated with top researchers, engineers, and developers, fostering a culture of innovation and creativity in the projects he undertakes.

Conclusion: Ping Jiang's relentless pursuit of innovation and his passion for creating cutting-edge solutions have solidified his reputation as a trailblazer in the technology landscape of Plano, TX.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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