The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Nov. 25, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

David Gerald Farber, Plano, TX (US);

Ping Jiang, Plano, TX (US);

Brian K. Kirkpatrick, Allen, TX (US);

Douglas T. Grider, III, McKinney, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3212 (2013.01); H01L 21/02112 (2013.01); H01L 21/32051 (2013.01); H01L 21/32055 (2013.01); H01L 21/32137 (2013.01);
Abstract

A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.


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