Texas Instruments Corporation

Tokyo Electron Limited

Texax Instruments Incorporated

Ping Jiang

Jiong-Ping Lu

Robert Kraft

Francis Gabriel Celii

Guoqiang Xing

Yaw S Obeng

David Gerald Farber

Joe G Tran

Hyesook Hong

Haowen Bu

Douglas Ticknor Grider

Brian Keith Kirkpatrick

Shaofeng Yu

Ting Yiu Tsui

Yong Seok Choi

Kenneth Joseph Newton

William Wesley Dostalik

Lee Chen

Andrew Marshall

Mark H Somervell

Gregory Boyd Shinn

Andrew McKerrow

Eden M Zielinski

Clint Montgomery

Karen H R Kirmse

Jeannette Michelle Jacques

Daty Michael Rogers

Laura M Matz

Heungsoo Park

Rosa A Orozco-Teran

Fred Y Clark

Rob Kraft

Robyn R Carlson

James D Krouse

Hiromi Sakima

A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma.

Low damage low-k dielectric etch

A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Method of fabricating semiconductors

A method of evaluating at least one parameter of a first capacitor. The method couples a number of capacitors in a capacitor network to a common node, the number of capacitors comprising at least three capacitors. Further, the method first applies a first voltage range to the capacitor network for causing a first voltage drop across the first capacitor, and it evaluates the at least one parameter in response to the first voltage range. The method second applies a second voltage range to the capacitor network for causing a second voltage drop across the first capacitor, the second voltage drop greater than the first voltage drop, and it evaluates the at least one parameter in response to the second voltage range.

Capacitor combination stress testing

A method and system for treating a substrate using a ballistic electron beam is described, whereby the radial uniformity of the electron beam flux is adjusted by modulating the source radio frequency (RF) power. For example, a plasma processing system is described having a first RF power coupled to a lower electrode, which may support the substrate, a second RF power coupled to an upper electrode that opposes the lower electrode, and a negative high voltage direct current (DC) power coupled to the upper electrode to form the ballistic electron beam. The amplitude of the second RF power is modulated to affect changes in the uniformity of the ballistic electron beam flux.

Method and system for controlling the uniformity of a ballistic electron beam by RF modulation

A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Poison-free and low ULK damage integration scheme for damascene interconnects

A method for making a transistorthat includes using a transition metal nitride layerand/or a SOG layerto protect the source/drain regionsfrom silicidation during the silicidation of the gate electrode. The SOG layeris planarized to expose the transition metal nitride layeror the gate electrodebefore the gate silicidation process. If a transition metal nitride layeris used, then it is removed from the top of the gate electrodebefore the full silicidation of the gate electrode

FUSI integration method using SOG as a sacrificial planarization layer

A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the substrate including an etch-stop layer, a low-k dielectric layer, and a hardmask layer. The method further includes the steps of patterning a photoresist masking layer on the dielectric stack to define a plurality of feature defining regions and plasma processing the substrate in a plasma-based reactor, The processing step includes etching a plurality of features into the hardmask layer and at least a portion of the low-k dielectric layer and performing a plasma treatment process in situ in the plasma-based reactor, where the plasma treatment process includes flowing at least one hydrocarbon into the reactor and generating a plasma, where a mass flow rate of the hydrocarbon is at least 0.1 sccm. The method also includes forming a metal conductor in the plurality of features.

Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics

Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide () while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material () and/or sputtering.

Gas switching during an etch process to modulate the characteristics of the etch

A method and system for etching a substrate control selectivity of the etch process by modulating the gas specie of the reactants. The gas specie selectively form and etch a buffer layer that protects underlying etch stop materials thereby providing highly selective etch processes.

Etching systems and processing gas specie modulation

A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

Methods to facilitate etch uniformity and selectivity

The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (), among other possible steps, includes forming a polysilicon gate electrode over a substrate () and forming source/drain regions () in the substrate () proximate the polysilicon gate electrode. The method further includes forming a blocking layer () over the source/drain regions (), the blocking layer () comprising a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode ().

Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same

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Plano, TX, United States of America

Ping Jiang