The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2008
Filed:
Aug. 19, 2005
Ting Y. Tsui, Garland, TX (US);
Jeannette M. Jacques, Tallahassee, FL (US);
Robert Kraft, Plano, TX (US);
Ping Jiang, Plano, TX (US);
Ting Y. Tsui, Garland, TX (US);
Jeannette M. Jacques, Tallahassee, FL (US);
Robert Kraft, Plano, TX (US);
Ping Jiang, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.