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For the Inventor, By the Inventor

Lagrangeville, NY, United States of America

Philip Joseph Oldiges

This inventor holds 53 USPTO granted patents and 1 published patent application, primarily in FinFET Technology (CPC class H01L). Top assignees: International Business Machines Corporation, Globalfoundries Inc.. Active years: 2004-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Philip Joseph Oldiges. Retrieved from https://idiyas.com/inventor/philip-joseph-oldiges

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 53 

% Patents Active = 47.2

Average Co-Inventor Count = 4.5

ph-index = 7

Forward Citations = 217(Granted Patents)

Forward Citations (Not Self Cited) = 210(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Lagrangeville, VT (US) (2008)
  • Langrangeville, NY (US) (2011)
  • Larangeville, NY (US) (2013)
  • Hopewell Junction, NY (US) (2012 - 2014)
  • LaGrangeville, NY (US) (2004 - 2024)

Company Filing History:

goldMedal51 out of 166,325 
 
International Business Machines Corporation
 patents
silverMedal2 out of 5,671 
 
Globalfoundries Inc.
 patents

Years Active: 2004-2024

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Areas of Expertise:
FinFET
Vertical FET
MOSFET
Radiation Tolerance
Dielectric Isolation
Leakage Current
Soft Error Protection
Stressed Channel FET
Ultra-Thin Devices
Memory Access Transistor
Semiconductor Structures
High-k Metal Gate
53 patents (USPTO):Explore Patents
1. 11910731 - Embedded heater in a phase change memory material (2024-02-20),
2. 11152378 - Reducing error rates with alpha particle protection (2021-10-19),
3. 10957780 - Non-uniform gate dielectric for U-shape MOSFET (2021-03-23),
4. 10468524 - Vertical field effect transistor with improved reliability (2019-11-05),
5. 10438949 - Vertical FET with reduced parasitic capacitance (2019-10-08),
6. 10297688 - Vertical field effect transistor with improved reliability (2019-05-21),
7. 10283504 - Vertical FET with reduced parasitic capacitance (2019-05-07),
8. 10256319 - Non-uniform gate dielectric for U-shape MOSFET (2019-04-09),
9. 10074652 - Vertical FET with reduced parasitic capacitance (2018-09-11),
10. 9853028 - Vertical FET with reduced parasitic capacitance (2017-12-26),
11. 9825094 - FinFET PCM access transistor having gate-wrapped source and drain regions (2017-11-21),
12. 9825093 - FinFET PCM access transistor having gate-wrapped source and drain regions (2017-11-21),
13. 9583624 - Asymmetric finFET memory access transistor (2017-02-28),
14. 9553173 - Asymmetric finFET memory access transistor (2017-01-24),
15. 9515171 - Radiation tolerant device structure (2016-12-06),

Title: The Inventor Philip Joseph Oldiges

Introduction: Philip Joseph Oldiges is a renowned inventor based in Lagrangeville, NY (US), known for his groundbreaking contributions to various fields through his innovative creations.

Latest Patents: Philip Joseph Oldiges holds several patents in diverse areas, showcasing his versatility and creativity in inventing new solutions to existing problems.

Career Highlights: Throughout his career, Philip Joseph Oldiges has demonstrated a keen ability to identify gaps in the market and develop unique inventions to address them. His passion for innovation has led to the successful commercialization of several of his inventions.

Collaborations: Philip Joseph Oldiges has collaborated with leading companies and research institutions to further develop and refine his inventions. These collaborations have resulted in the creation of cutting-edge technologies that have had a significant impact on their respective industries.

Conclusion: Philip Joseph Oldiges continues to be a driving force in the world of innovation, constantly pushing the boundaries of what is possible through his inventive spirit and dedication to creating a better future through his inventions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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