International Business Machines Corporation

Globalfoundries Inc.

Philip Joseph Oldiges

Bruce Bennett Doris

Huilong Zhu

Chung-Hsun Lin

Kangguo Cheng

Dechao Guo

Xinlin Wang

Chen Zhang

Xin Miao

Wenyu Xu

Pranita Kulkarni

Ethan Harrison Cannon

Darsen D Lu

Ying Di Zhang

Huajie Chen

Chung H Lam

Tak H Ning

Ramachandran Muralidhar

Richard Quimby Williams

Viorel C Ontalus

Alvin Wayne Strong

John M Aitken

Ghavam G Shahidi

Oleg Gluschenkov

Hailing Wang

Wilfried Ernest-August Haensch

Effendi Leobandung

Dureseti Chidambarrao

Keith Kwong Hon Wong

Shu-Jen Han

Kern Rim

Jeffrey Bowman Johnson

Pranita Kerber

Meikei Ieong

Min Yang

Dieter F Wendel

Jochen C Beintner

James Douglas Warnock

K Paul Muller

Yanfeng Wang

Leon Jacob Sigal

Aj KleinOsowski

Kai Xiu

Wilfried E A Haensch

Cheruvu Suryanarayana Murthy

Alexander Reznicek

Ali Khakifirooz

Mark Charles Hakey

Fei Liu

Xin Ru Wang

Kenneth Parker Rodbell

Paul Michael Solomon

Elbert Emin Huang

Tze-Chiang Chen

Hussein Ibrahim Hanafi

Robert L Wisnieff

Robert L Bruce

Leathen Shi

Daniel Lawrence Stasiak

Christy Sensenich Tyberg

Erin C Jones

Jin Ping Han

Satya N Chakravarti

Ching-Tzu Chen

Gan Wang

Wilfried Ernst-August Haensch

Henry H K Tang

Hassan Naser

Michael J Mueller

A J Kleinosowski

A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

Embedded heater in a phase change memory material

An integrated circuit package with a buffer providing radiation protection to memory elements and components is described. The integrated circuit packages and the incorporated buffers provide a protective distance between potential sources of internal radiation particles within the integrated circuit package and any memory elements/components which may be sensitive to radiation such as alpha particles. This protective distance allows for the integrated circuit packages to be completed or assembled without needing added more expensive or redundant memory components.

Reducing error rates with alpha particle protection

A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.

Non-uniform gate dielectric for U-shape MOSFET

Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin. Removing the liner including the first dielectric material includes exposing portions of the source/drain region. The method further includes forming a spacer layer on the second dielectric material and portions of the source/drain region exposed by removing the liner including the first dielectric material and forming a gate material on the spacer layer.

Vertical field effect transistor with improved reliability

A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

Vertical FET with reduced parasitic capacitance

Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

FinFET PCM access transistor having gate-wrapped source and drain regions

A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged on the doped source layer, a fin arranged on the insulator layer, a source region extension portion extending from the doped source layer and through the fin, a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion, a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.

Asymmetric finFET memory access transistor

Techniques for producing radiation tolerant device structures are provided. In one aspect, a method for forming a radiation-hardened device includes the steps of: forming fin masks on a SOI layer of an SOI wafer, wherein the SOI wafer includes the SOI layer separated from a substrate by a buried insulator; patterning fins in the SOI layer using the fin masks; and implanting at least one dopant into exposed portions of the buried insulator between the fins to increase a radiation hardness of the device structure by providing a path in the buried insulator for charge to dissipate, wherein the fin masks are left in place during the implanting step to prevent damage to the fins. Implementations with a bulk substrate, as well as the resulting devices, are also provided.

Radiation tolerant device structure

Growing community of inventors

Lagrangeville, NY, United States of America

Philip Joseph Oldiges