The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Apr. 30, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Xin Miao, Guilderland, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Wenyu Xu, Albany, NY (US);

Chen Zhang, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/66666 (2013.01);
Abstract

Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin. Removing the liner including the first dielectric material includes exposing portions of the source/drain region. The method further includes forming a spacer layer on the second dielectric material and portions of the source/drain region exposed by removing the liner including the first dielectric material and forming a gate material on the spacer layer.


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