Los Gatos, CA, United States of America

Peter P Cuevas

This inventor holds 17 USPTO granted patents and 2 published patent applications and 1 EPO patent, primarily in Semiconductor Testing. Top assignees: Qualitau, Inc., Integrated Silicon Solution, (Cayman) Inc., Spin Memory, Inc.. Active years: 2000-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Peter P Cuevas. Retrieved from https://idiyas.com/inventor/peter-p-cuevas

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17 

% Patents Active = 100.0


Average Co-Inventor Count = 1.9

ph-index = 4

Forward Citations = 44(Granted Patents)


Company Filing History:


Years Active: 2000-2023

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Areas of Expertise:
DRAM
Selector Transistor
Epitaxial Cell
Buried Bitline
Current Drive
Redundant Memory
Test Socket
Zero Insertion Force
Programmable Connector
Measurement Unit
Pulsed Current Generator
Electrical Connector
17 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Peter P Cuevas

Introduction

Peter P Cuevas is a prominent inventor based in Los Gatos, California. He has made significant contributions to the field of semiconductor technology, holding a total of 17 patents. His work focuses on advancements in memory devices, particularly dynamic random access memory (DRAM) and magnetic memory structures.

Latest Patents

One of his latest patents is for a DRAM with a selective epitaxial cell transistor. This invention outlines a method for manufacturing a dynamic random access memory device, which includes providing a semiconductor substrate and forming a highly doped diffusion region in its surface. A wordline structure is deposited on the substrate, incorporating an electrically conductive gate layer. An opening is formed in the wordline structure, extending to the highly doped diffusion region. A semiconductor pillar is then created in this opening through selective epitaxial growth, with a doped end connected to a memory element.

Another notable patent is for a selector transistor with continuously variable current drive. This magnetic memory structure features a two-terminal resistive memory element connected to a selector structure. The selector structure includes a semiconductor pillar formed on a substrate, surrounded by a gate dielectric layer and an electrically conductive gate structure. The semiconductor pillar has unequal dimensions in a plane parallel to the substrate surface, allowing for adjustable current flow to drive the resistive memory element.

Career Highlights

Peter has worked with several companies throughout his career, including Qualitau, Inc. and Integrated Silicon Solution, Inc. His experience in these organizations has contributed to his expertise in semiconductor technologies and memory devices.

Collaborations

Peter has collaborated with notable professionals in the field, including Amitay Levi and Andrew J Walker. These collaborations have further enhanced his innovative contributions to semiconductor technology.

Conclusion

Peter P Cuevas is a distinguished inventor whose work in semiconductor technology has led to significant advancements in memory devices. His patents reflect a deep understanding of the complexities involved in memory manufacturing and design. His contributions continue to influence the field and inspire future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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