The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Mar. 24, 2020
Applicant:

Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;

Inventors:

Andrew J. Walker, Mountain View, CA (US);

Dafna Beery, Palo Alto, CA (US);

Peter Cuevas, Los Gatos, CA (US);

Amitay Levi, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/3065 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 27/10855 (2013.01); H01L 27/10873 (2013.01); H01L 29/1037 (2013.01); H01L 29/42356 (2013.01); H01L 29/45 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.


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