The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Jan. 28, 2020
Applicant:

Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;

Inventors:

Andrew J. Walker, Mountain View, CA (US);

Dafna Beery, Palo Alto, CA (US);

Peter Cuevas, Los Gatos, CA (US);

Amitay Levi, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/108 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/161 (2006.01); H01L 29/20 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10808 (2013.01); H01L 27/10855 (2013.01); H01L 27/10873 (2013.01); H01L 27/10891 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/66522 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.


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