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For the Inventor, By the Inventor

Essex Junction, VT, United States of America

Peter James Lindgren

This inventor holds 34 USPTO granted patents and 1 published patent application and 2 EPO patents, primarily in Semiconductor Fabrication. Top assignees: International Business Machines Corporation, Globalfoundries U.S. 2 LLC, Ultratech, Inc.. Active years: 2002-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Peter James Lindgren. Retrieved from https://idiyas.com/inventor/peter-james-lindgren

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 34 

% Patents Active = 52.9


Average Co-Inventor Count = 3.9

ph-index = 6

Forward Citations = 184(Granted Patents)


Location History:

  • Burlington, VT (US) (2002 - 2010)
  • Essex Junction, VT (US) (2004 - 2015)

Company Filing History:

goldMedal32 out of 166,409 
 
International Business Machines Corporation
 patents
silverMedal1 out of 59 
 
Globalfoundries U.S. 2 LLC
 patents
bronzeMedal1 out of 138 
 
Ultratech, Inc.
 patents

Years Active: 2002-2015

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Areas of Expertise:
Dual-Damascene Process
RF Switch
High-Density Capacitors
Through Silicon Vias
Inductor Design
Metal Wiring Structure
Silicided Trench Contact
Substrate Via
Lithographic Alignment
Microtrenching
Dishing Correction
Cobalt Disilicide
34 patents (USPTO):Explore Patents
1. 9171778 - Dual-damascene process to fabricate thick wire structure (2015-10-27),
2. 8872281 - Silicided trench contact to buried conductive layer (2014-10-28),
3. 8753950 - Dual-damascene process to fabricate thick wire structure (2014-06-17),
4. 8748207 - Hybrid MEMS RF switch and method of fabricating same (2014-06-10),
5. 8722508 - Low harmonic RF switch in SOI (2014-05-13),
6. 8674472 - Low harmonic RF switch in SOI (2014-03-18),
7. 8674423 - Semiconductor structure having vias and high density capacitors (2014-03-18),
8. 8645898 - Structure and design structure for high-Q value inductor and method of manufacturing the same (2014-02-04),
9. 8643190 - Through substrate via including variable sidewall profile (2014-02-04),
10. 8631570 - Through wafer vias with dishing correction methods (2014-01-21),
11. 8445306 - Hybrid MEMS RF switch and method of fabricating same (2013-05-21),
12. 8338265 - Silicided trench contact to buried conductive layer (2012-12-25),
13. 8293638 - Method of fabricating damascene structures (2012-10-23),
14. 8236663 - Dual-damascene process to fabricate thick wire structure (2012-08-07),
15. 8234606 - Metal wiring structure for integration with through substrate vias (2012-07-31),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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