The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2012
Filed:
Apr. 06, 2011
David S. Collins, Williston, VT (US);
Alvin Joseph, Williston, VT (US);
Peter J. Lindgren, Essex Junction, VT (US);
Anthony K. Stamper, Williston, VT (US);
Kimball M. Watson, Essex Junction, VT (US);
David S. Collins, Williston, VT (US);
Alvin Joseph, Williston, VT (US);
Peter J. Lindgren, Essex Junction, VT (US);
Anthony K. Stamper, Williston, VT (US);
Kimball M. Watson, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.