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For the Inventor, By the Inventor

Wappingers Falls, NY, United States of America

Paul Christian Parries

This inventor holds 57 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Manufacturing (CPC class H01L). Top assignees: International Business Machines Corporation, Globalfoundries Inc., Infineon Technologies Ag. Active years: 1989-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Paul Christian Parries. Retrieved from https://idiyas.com/inventor/paul-christian-parries

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 57 

% Patents Active = 70.2

Average Co-Inventor Count = 4.9

ph-index = 10

Forward Citations = 430(Granted Patents)

Forward Citations (Not Self Cited) = 408(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Essex Junction, VT (US) (1989 - 1997)
  • Wapingers Falls, NY (US) (2004)
  • Wappinger Falls, NY (US) (2006)
  • Hopewell Junction, NY (US) (2012 - 2014)
  • Wappingers Falls, NY (US) (1995 - 2016)
  • Beacon, NY (US) (2013 - 2016)

Company Filing History:

goldMedal50 out of 166,409 
 
International Business Machines Corporation
 patents
silverMedal2 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal1 out of 15,036 
 
Infineon Technologies Ag
 patents
4. 1 out of 30,886 
 
Siemens Aktiengesellschaft
 patents
5. 1 out of 32 
 
Siemens Components, Inc.
 patents
6. 5 out of 834,570 
Other
 patents
where one patent can have more than one assignee

Years Active: 1989-2016

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Areas of Expertise:
SOI Device
Deep Trench Capacitors
DRAM Technologies
Threshold Voltage
Isolation Structures
Stress Induced Shifts
Capacitor Fabrication
Low Power Management
Memory Circuits
Back Channel Leakage
Polysilicon Contact Resistance
57 patents (USPTO):Explore Patents
1. 9484269 - Structure and method to control bottom corner threshold in an SOI device (2016-11-01),
2. 9311443 - Correcting for stress induced pattern shifts in semiconductor manufacturing (2016-04-12),
3. 9240482 - Asymmetric stressor DRAM (2016-01-19),
4. 9136321 - Low energy ion implantation of a junction butting region (2015-09-15),
5. 9087927 - Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches (2015-07-21),
6. 8963283 - Method of fabricating isolated capacitors and structure thereof (2015-02-24),
7. 8940617 - Method of fabricating isolated capacitors and structure thereof (2015-01-27),
8. 8901706 - [object Object] (2014-12-02),
9. 8835994 - Reduced corner leakage in SOI structure and method (2014-09-16),
10. 8809953 - FET structures with trench implantation to improve back channel leakage and body resistance (2014-08-19),
11. 8741780 - Reduced corner leakage in SOI structure and method (2014-06-03),
12. 8723243 - Polysilicon/metal contact resistance in deep trench (2014-05-13),
13. 8716776 - Method of fabricating isolated capacitors and structure thereof (2014-05-06),
14. 8652933 - Semiconductor structure having wide and narrow deep trenches with different materials (2014-02-18),
15. 8652925 - Method of fabricating isolated capacitors and structure thereof (2014-02-18),

Title: Innovations of Paul Christian Parries: A Pioneer in Semiconductor Technology

Introduction

Paul Christian Parries, based in Wappingers Falls, NY, is a notable inventor with an impressive portfolio of 57 patents. His innovations primarily focus on semiconductor structures and methods that have significantly contributed to advancements in the field.

Latest Patents

Among his most recent patents are two groundbreaking inventions:

1. **Structure and Method to Control Bottom Corner Threshold in an SOI Device**

This innovation revolves around semiconductor structures and methods tailored to control the bottom corner threshold in a silicon-on-insulator (SOI) device. The method involves doping a corner region of a semiconductor-on-insulator island. This localized doping is designed to reduce capacitive coupling with adjacent structures, enhancing the performance and efficiency of SOI devices.

2. **Correcting for Stress Induced Pattern Shifts in Semiconductor Manufacturing**

This patent details an apparatus, method, and computer program product that addresses the challenge of reducing overlay errors during the semiconductor photolithographic mask design process. The method predicts stress-induced displacements by analyzing data on density characteristics of a photomask layout. It then corrects the design by adjusting individual photo mask shapes in anticipation of these predicted displacements, ultimately improving manufacturing accuracy.

Career Highlights

Throughout his career, Paul has worked with prestigious companies, notably IBM, where he contributed to significant advancements in semiconductor technologies. His extensive experience in the industry has solidified his reputation as a leading innovator.

Collaborations

Paul has collaborated with talented individuals such as Geng Wang and Chengwen Pei, showcasing his ability to work alongside other skilled professionals to drive innovation in semiconductor research.

Conclusion

Paul Christian Parries stands out as a pioneering inventor whose contributions to semiconductor technology are reflected in his numerous patents. His innovative methodologies and collaborative efforts continue to shape the future of the industry, benefiting both manufacturers and consumers alike.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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