International Business Machines Corporation

Other

Globalfoundries Inc.

Siemens Aktiengesellschaft

Infineon Technologies Ag

Siemens Components, Inc.

Paul Christian Parries

Geng Wang

Chengwen Pei

Yanli Zhang

Jeffrey Bowman Johnson

Herbert Lei Ho

Oh-Jung Kwon

John Edward Barth, Jr

Kangguo Cheng

Joseph Ervin

Junedong Lee

Subramanian Srikanteswara Iyer

Johnathan E Faltermeier

Dominic Joseph Schepis

Babar Ali Khan

Matthew R Wordeman

Christopher Carr Parks

Kevin McStay

Jack Allan Mandelman

Toshiaki Kirihata

Randy William Mann

William Robert Reohr

Johann Alsmeier

Gregory J Fredeman

James Anthony O'Neill

John W Golz

Ramachandra Divakaruni

Charles W Koburger, Iii

Michael Patrick Chudzik

Shreesh Narasimha

Bomy A Chen

Siddarth A Krishnan

Rajarao Jammy

Ulrike Gruening

David Michael Fried

Ravi Mahendra Todi

Abhishek Dube

Rishikesh Krishnan

Max Gerald Levy

Hongwen Yan

Kevin R Winstel

George R Goth

Gerd Pfeiffer

Paul Andrew Ronsheim

Gan Wang

Hoki Kim

Brian W Messenger

Katsunori Onishi

Maryjane Brodsky

Bachir Dirahoui

Brent A Anderson

John Edward Cronin

Louis L Hsu

Rajiv V Joshi

Dureseti Chidambarrao

Arne Watson Ballantine

Wendell P Noble

Douglas Duane Coolbaugh

Wayne Frederick Ellis

Pranita Kulkarni

Tze-Chiang Chen

Albert Manhee Chu

John Kenneth DeBrosse

Yun-Yu Wang

Christopher Joseph Waskiewicz

Kwong Hon Wong

Thomas L McDevitt

James Gardner Ryan

Donald M Kenney

Jerome Brett Lasky

James A Culp

Howard Smith Landis

Kevin William Gorman

Karen A Nummy

Kenneth John Giewont

Rosemary A Previti-Kelly

David R Hanson

Deok-kee Kim

Carter W Kaanta

Francis Roger White

Matthew J Sendelbach

Robert E Busch

Norman Whitelaw Robson

Mark David Jacunski

Ezra D B Hall

Philip L Flaitz

Peter Stevens Locke

William C Wille

Ricky S Amos

Rick L Mohler

Jin J Wu

Brian J Machesney

Chorng-Lii Hwang

David Craig Strippe

Yoichi Otani

Thomas J Licata

Victor R Nastasi

Teresa Jacqueline Wu

James Patrick Norum

Alan D Norris

Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.

Structure and method to control bottom corner threshold in an SOI device

Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Correcting for stress induced pattern shifts in semiconductor manufacturing

A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

Asymmetric stressor DRAM

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

Low energy ion implantation of a junction butting region

A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Method of fabricating isolated capacitors and structure thereof

[object Object]

A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

Reduced corner leakage in SOI structure and method

A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

FET structures with trench implantation to improve back channel leakage and body resistance

A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

Polysilicon/metal contact resistance in deep trench

Disclosed is a method of forming a semiconductor device structure in a semiconductor layer. The method includes forming a first trench of a first width and a second trench of a second width in the semiconductor layer; depositing a layer of first material which conforms to a wall of the first trench but does not fill it and which fills the second trench; removing the first material from the first trench, the first material remaining in the second trench; depositing a second material into and filling the first trench and over a top of the first material in the second trench; and uniformly removing the second material from the top of the first material in the second trench, wherein the first trench is filled with the second material and the second trench is filled with the first material and wherein the first material is different from the second material.

Semiconductor structure having wide and narrow deep trenches with different materials

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Wappingers Falls, NY, United States of America

Paul Christian Parries