The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2014
Filed:
Mar. 21, 2012
David M. Fried, Brewster, NY (US);
Jeffrey B. Johnson, Essex Junction, VT (US);
Kevin Mcstay, Hopewell Junction, NY (US);
Paul Parries, Wappingers Falls, NY (US);
Chengwen Pei, Danbury, CT (US);
Gan Wang, Fishkill, NY (US);
Geng Wang, Stormville, NY (US);
Yanli Zhang, San Jose, CA (US);
David M. Fried, Brewster, NY (US);
Jeffrey B. Johnson, Essex Junction, VT (US);
Kevin McStay, Hopewell Junction, NY (US);
Paul Parries, Wappingers Falls, NY (US);
Chengwen Pei, Danbury, CT (US);
Gan Wang, Fishkill, NY (US);
Geng Wang, Stormville, NY (US);
Yanli Zhang, San Jose, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.