The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
Apr. 30, 2014
International Business Machines Corporation, Armonk, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Katsunori Onishi, Somers, NY (US);
Paul C. Parries, Beacon, NY (US);
Chengwen Pei, Danbury, CT (US);
Geng Wang, Stormville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.