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For the Inventor, By the Inventor

Lafayette, CA, United States of America

Paul C Lindsey, Jr

This inventor holds 13 USPTO granted patents. Top assignees: Micro Processing Technology, Inc., Motorola Corporation, Other. Active years: 1981-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Paul C Lindsey, Jr. Retrieved from https://idiyas.com/inventor/paul-c-lindsey-jr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 13

% Patents Active = 38.5

Average Co-Inventor Count = 1.5

ph-index = 7

Forward Citations = 150(Granted Patents)


Company Filing History:

goldMedal10 out of 10 
 
Micro Processing Technology, Inc.
 patents
silverMedal1 out of 20,290 
 
Motorola Corporation
 patents
bronzeMedal2 out of 834,570 
Other
 patents

Years Active: 1981-2018

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13 patents (USPTO):Explore Patents
1. 10056297 - Modified plasma dicing process to improve back metal cleaving (2018-08-21),
2. 9153493 - System for separating devices from a semiconductor wafer (2015-10-06),
3. 8906745 - Method using fluid pressure to remove back metal from semiconductor wafer scribe streets (2014-12-09),
4. 8450188 - Method of removing back metal from an etched semiconductor scribe street (2013-05-28),
5. 8445361 - Method of dividing a semiconductor wafer having semiconductor and metal layers into separate devices (2013-05-21),
6. 8220685 - System for breaking a semiconductor wafer or other workpiece along a scribe line (2012-07-17),
7. 7807479 - Method and apparatus for improving force control in wafer scribing (2010-10-05),
8. 7415916 - Scribing system with particle remover (2008-08-26),
9. 7392732 - Scribing tool and method (2008-07-01),
10. 7165331 - Apparatus and method for scribing a semiconductor wafer while controlling scribing forces (2007-01-23),
11. 6826840 - Semiconductor wafer scribing system (2004-12-07),
12. 6022807 - Method for fabricating an integrated circuit (2000-02-08),
13. 4264393 - Reactor apparatus for plasma etching or deposition (1981-04-28),

Title: Paul C Lindsey, Jr: Innovator in Semiconductor Technology

Introduction

Paul C Lindsey, Jr. is a notable inventor based in Lafayette, CA (US), recognized for his contributions to semiconductor technology. With a total of 13 patents to his name, Lindsey has made significant advancements in the field, particularly in processes that enhance the efficiency of semiconductor manufacturing.

Latest Patents

Among his latest patents is a modified plasma dicing process aimed at improving back metal cleaving. This innovative method enhances the cleaving of the back metal along the edges of semiconductor wafers mounted on deformable plastic films. The process includes depositing a layer of material on the metal located on the wafer's backside in etched streets. Another significant patent is a system for separating devices from a semiconductor wafer. This system allows for the separation of semiconductor devices from a wafer with back metal exposed in scribe streets, utilizing a variable radial force to stretch and tension the film while controlling these parameters effectively.

Career Highlights

Throughout his career, Paul C Lindsey, Jr. has worked with various companies, including Micro Processing Technology, Inc. His work has been instrumental in developing innovative solutions that address challenges in semiconductor manufacturing.

Collaborations

Lindsey has collaborated with notable professionals in the industry, including Jeffery D Atkinson and Darrell W Foote. Their combined expertise has contributed to the successful development of various technologies in the semiconductor field.

Conclusion

Paul C Lindsey, Jr. stands out as a significant figure in semiconductor innovation, with a strong portfolio of patents that reflect his dedication to advancing technology. His work continues to influence the industry and pave the way for future developments.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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