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For the Inventor, By the Inventor

San Jose, CA, United States of America

Padmapani Nallan

USPTO Granted Patents = 33

Average Co-Inventor Count = 2.9

ph-index = 14

Forward Citations = 722(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (2000 - 2003)
  • San Jose, CA (US) (2002 - 2010)

Company Filing History:

goldMedal23 out of 13,684 
 
Applied Materials, Inc.
 patents
silverMedal10 out of 832,680 
Other
 patents

Years Active: 2000-2010

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33 patents (USPTO):Explore Patents
1. 7838434 - Method of plasma etching of high-K dielectric materials (2010-11-23),
2. 7320942 - Method for removal of metallic residue after plasma etching of a metal layer (2008-01-22),
3. 7217665 - Method of plasma etching high-K dielectric materials with high selectivity to underlying layers (2007-05-15),
4. 7105361 - Method of etching a magnetic material (2006-09-12),
5. 7094704 - Method of plasma etching of high-K dielectric materials (2006-08-22),
6. 6984585 - Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer (2006-01-10),
7. 6964928 - Method for removing residue from a magneto-resistive random access memory (MRAM) film stack using a dual mask (2005-11-15),
8. 6943039 - Method of etching ferroelectric layers (2005-09-13),
9. 6942813 - Method of etching magnetic and ferroelectric materials using a pulsed bias source (2005-09-13),
10. 6902681 - Method for plasma etching of high-K dielectric materials (2005-06-07),
11. 6893893 - Method of preventing short circuits in magnetic film stacks (2005-05-17),
12. 6855643 - Method for fabricating a gate structure (2005-02-15),
13. 6806095 - Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers (2004-10-19),
14. 6767824 - Method of fabricating a gate structure of a field effect transistor using an alpha-carbon mask (2004-07-27),
15. 6759340 - Method of etching a trench in a silicon-on-insulator (SOI) structure (2004-07-06),

Title: Innovator Spotlight: Padmapani Nallan

Introduction:

Padmapani Nallan, a prolific inventor based in San Jose, CA, has made significant contributions to the field of semiconductor technology. With an impressive portfolio of 33 patents, his innovative work has revolutionized processes in the industry.

Latest Patents:

Among his latest patents is the "Method of plasma etching of high-K dielectric materials," which outlines a novel technique for etching high dielectric constant materials using a strategic gas chemistry mix. Additionally, Nallan developed the "Method for removal of metallic residue after plasma etching of a metal layer," showcasing his expertise in substrate cleaning post-plasma etch processes.

Career Highlights:

Padmapani Nallan has garnered valuable experience working at prestigious companies such as Applied Materials, Inc., where he honed his skills and expertise in semiconductor manufacturing processes. His inventive solutions have significantly impacted the efficiency and effectiveness of semiconductor fabrication.

Collaborations:

Throughout his career, Nallan has collaborated with esteemed professionals in the industry, including Ajay Kumar and Chentsau Chris Ying. These collaborations have led to groundbreaking innovations and advancements in semiconductor technology.

Conclusion:

In conclusion, Padmapani Nallan stands out as a visionary inventor who continues to push the boundaries of semiconductor technology. His remarkable portfolio of patents is a testament to his ingenuity and dedication to driving innovation in the field.

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